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Computer Architecture
Topic: Speculative Precomputation
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Publications for topic "Speculative Precomputation" sorted by title
A
| A study of source-level compiler algorithms for automatic construction of pre-execution code, and (2004), in: ACM Trans. Comput. Syst., 22:3(326--379) |
[DOI] |
C
| Compiler Based Pre-execution, , 2004 |
D
| Decoupled Software Pipelining with the Synchronization Array, , , and , in: PACT '04: Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pages 177--188, IEEE Computer Society, 2004 |
[DOI] |
| Design and evaluation of compiler algorithms for pre-execution, and , in: ASPLOS-X: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, pages 159--170, ACM Press, 2002 |
[DOI] |
E
| Extending OpenMP to Support Slipstream Execution Mode, and , in: IPDPS '03: Proceedings of the 16th International Symposium on Parallel and Distributed Processing, pages 36.2, IEEE Computer Society, 2003 |
F
| Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors, and , in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 350--360, IEEE Computer Society, 2005 |
[DOI] |
H
| Helper threads via virtual multithreading, , , , , , , , , and (2004), in: IEEE Micro, 24:6(74--82) |
[DOI] |
| Helper threads via virtual multithreading on an experimental itanium2 processor-based platform, , , , , , , , , and (2004), in: SIGOPS Oper. Syst. Rev., 38:5(144--155) |
[DOI] |
P
| Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors, , , , , , , , , and , in: CGO '04: Proceedings of the International Symposium on Code Generation and Optimization, Palo Alto, California, pages 27, IEEE Computer Society, 2004 |
S
| Simultaneous subordinate microthreading (SSMT), , , , and (1999), in: ISCA '99: Proceedings of the 26th annual international symposium on Computer architecture:2(186--195) |
[DOI] |
| Slipstream execution mode for CMP-based multiprocessors, , and , in: HPCA '03: Proceedings of the IEEE 9th International Symposium on High Performance Computer Architecture, pages 179--190, 2003 |
[DOI] |
| Speculative Precomputation on Chip Multiprocessors, , , , and , in: MTEAC-6 : 6th Workshop on Multithreaded Execution, Architecture, and Compilation, 2002 |
| Speculative precomputation: long-range prefetching of delinquent loads, , , , , , and , in: ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, G\&\#246;teborg, Sweden, pages 14--25, ACM Press, 2001 |
[DOI] |
T
| Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors, , in: ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, G\&\#246;teborg, Sweden, pages 40--51, ACM Press, 2001 |
[DOI] |
| Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance, and , in: PACT '02: Proceedings of the 11th international conference on Parallel architectures and compilation techniques, pages 30, IEEE Computer Society, 2002 |
U
| Using Program Slicing to Drive Pre-Execution on Simultaneous Multithreading Processors, and , University of Maryland, 2001 |