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multicore

Publications for keyword "multicore"
2008
Understanding the Overhead of the Spin-Lock Loop in CMT Architectures, Javier VerdĂș Vladimir Cakarevic, Petar Radojkovic and Mateo Valero, in: WIOSCA '08: In Procs. of Workshop on the Interaction between Operating Systems and Computer Architecture, 2008
2007
Scheduling threads for constructive cache sharing on CMPs, Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry and Chris Wilkerson, in: SPAA '07: Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures, San Diego, California, USA, pages 105--115, ACM, 2007
[DOI]
2006
Exploiting Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors, Matthew DeVuyst, Rakesh Kumar and Dean M. Tullsen, in: IPDPS '06: Proceedings of the 20th International Symposium on Parallel and Distributed Processing, 2006
2005
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors, Yonghong Song, Spiros Kalogeropulos and Partha Tirumalai, in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 99--109, IEEE Computer Society, 2005
[DOI]
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window, Huiyang Zhou, in: PACT '05: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, pages 231--242, IEEE Computer Society, 2005
[DOI]
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors, Ilya Ganusov and Martin Burtscher, in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 350--360, IEEE Computer Society, 2005
[DOI]
Optimizing Compiler for the CELL Processor, A. E. Eichenberger, K. O'Brien, Peng Wu, Tong Chen, P. H. Oden, D. A. Prener, J. C. Shepherd, Byoungro So, Z. Sura, A. Wang, Tao Zhang, Peng Zhao and M. Gschwind, in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 161-172, 2005
[DOI]
2004
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy, Eric Tune, Rakesh Kumar, Dean M. Tullsen and Brad Calder, in: MICRO 37: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, Portland, Oregon, pages 183--194, IEEE Computer Society, 2004
[DOI]
2003
1998
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization, J. Greggory Steffan and Todd C. Mowry, in: HPCA '98: Proceedings of the IEEE 4th International Symposium on High Performance Computer Architecture, pages 2--13, 1998

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1997
A Single-Chip Multiprocessor, Lance Hammond, Basem A. Nayfeh and Kunle Olukotun (1997), in: Computer, 30:9(79--85)

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