multicore
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Publications for keyword "multicore"
2008
Larrabee: a many-core x86 architecture for visual computing, , , , , , , , , , , , , and , in: SIGGRAPH '08: ACM SIGGRAPH 2008 papers, Los Angeles, California, pages 1--15, ACM, 2008 |
[DOI] |
Understanding the Overhead of the Spin-Lock Loop in CMT Architectures, and , in: WIOSCA '08: In Procs. of Workshop on the Interaction between Operating Systems and Computer Architecture, 2008 |
2007
IBM POWER6 microarchitecture, , , , , , , , and (2007), in: IBM J. Res. Dev., 51:6(639--662) |
Scheduling threads for constructive cache sharing on CMPs, , , , , , , , , , and , in: SPAA '07: Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures, San Diego, California, USA, pages 105--115, ACM, 2007 |
[DOI] |
2006
Exploiting Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors, , and , in: IPDPS '06: Proceedings of the 20th International Symposium on Parallel and Distributed Processing, 2006 |
2005
An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors, , , and , in: IWOMP '05: International Workshop on OpenMP, 2005 |
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors, , and , in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 99--109, IEEE Computer Society, 2005 |
[DOI] |
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window, , in: PACT '05: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, pages 231--242, IEEE Computer Society, 2005 |
[DOI] |
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors, and , in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 350--360, IEEE Computer Society, 2005 |
[DOI] |
Montecito: a dual-core, dual-thread Itanium processor, (2005), in: IEEE Micro, 25:2(10-20) |
[DOI] |
Niagara: a 32-way multithreaded Sparc processor, , and (2005), in: IEEE Micro, 25:2(21-29) |
[DOI] |
Optimizing Compiler for the CELL Processor, , , , , , , , , , , , and , in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 161-172, 2005 |
[DOI] |
2004
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy, , , and , in: MICRO 37: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, Portland, Oregon, pages 183--194, IEEE Computer Society, 2004 |
[DOI] |
IBM Power5 chip: a dual-core multithreaded processor, (2004), in: IEEE Micro, 24:2(40-47) |
[DOI] |
2003
The AMD Opteron processor for multiprocessor servers, (2003), in: IEEE Micro, 23:2(66-76) |
[DOI] |
1998
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization, and , in: HPCA '98: Proceedings of the IEEE 4th International Symposium on High Performance Computer Architecture, pages 2--13, 1998 |
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1997
A Single-Chip Multiprocessor, , and (1997), in: Computer, 30:9(79--85) |
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