Keywords:
Publications of Mateo Valero sorted by first author
B
| Software-Controlled Priority Characterization of POWER5 Processor, , , , , and (2008), in: SIGARCH Comput. Archit. News, 36:3(415--426) |
[DOI] |
C
| Predictable performance in SMT processors, , , , , and , in: CF '04: Proceedings of the 1st conference on Computing frontiers, Ischia, Italy, pages 433--443, ACM Press, 2004 |
[DOI] |
| Dynamically Controlled Resource Allocation in SMT Processors, , , and , in: MICRO 37: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, Portland, Oregon, pages 171--182, IEEE Computer Society, 2004 |
[DOI] |
G
| A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies, , , and |
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H
| Transactional Memory: An Overview, , , , , , and , pages 8--29, IEEE Computer Society Press, 2007 |
[DOI] |
V
| Understanding the Overhead of the Spin-Lock Loop in CMT Architectures, and , in: WIOSCA '08: In Procs. of Workshop on the Interaction between Operating Systems and Computer Architecture, 2008 |