Topic: Computer Architecture - Cslab Bibliography Portal

Niagara: a 32-way multithreaded Sparc processor, P. Kongetira, K. Aingaran and Kunle Olukotun (2005), in: IEEE Micro, 25:2(21-29)

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Omni OpenMP Compiler Project, Released in the International Conference for High Performance Computing, Networking and Storage (SC'03), 2003

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Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations (2006), in: IEEE Trans. Comput., 55:3(268--280)

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Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures, Weirong Zhu, Vugranam C Sreedhar, Ziang Hu and Guang R. Gao, in: ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture, San Diego, California, USA, pages 35--45, ACM, 2007

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On the Role of Deterministic Fine-Grain Data Synchronization for Scientific Applications: A Revisit in the Emerging Many-Core Era, Weirong Zhu, Ziang Hu and Gao G.R., in: IPDPS '07: Proceedings of the 20th International Symposium on Parallel and Distributed Processing, pages 1--8, 2007

[DOI]

Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window, Huiyang Zhou, in: PACT '05: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, pages 231--242, IEEE Computer Society, 2005

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An Adaptive OpenMP Loop Scheduler for Hyperthreaded SMPs, Yun Zhang, Mihai Burcea, Victor Cheng, Ron Ho and Michael Voss, in: PDCS '04, 2004

Accelerating and Adapting Precomputation Threads for Effcient Prefetching, Weifeng Zhang, Dean M. Tullsen and Brad Calder, in: HPCA '07: Proceedings of the IEEE 13th International Symposium on High Performance Computer Architecture, pages 85--95, IEEE Computer Society, 2007

[DOI]

A Study of a Transactional Parallel Routing Algorithm, Ian Watson, Chris Kirkham and Mikel Lujan, in: PACT '07: Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques, pages 388--398, IEEE Computer Society, 2007

[DOI]

Runtime support for integrating precomputation and thread-level parallelism on simultaneous multithreaded processors, Tanping Wang, Filip Blagojevic and Dimitrios S. Nikolopoulos, in: LCR '04: Proceedings of the 7th workshop on Workshop on languages, compilers, and run-time support for scalable systems, Houston, Texas, pages 1--12, ACM Press, 2004

[DOI]

Helper threads via virtual multithreading on an experimental itanium2 processor-based platform, Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore and John P. Shen (2004), in: SIGOPS Oper. Syst. Rev., 38:5(144--155)

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Helper threads via virtual multithreading, Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore and John P. Shen (2004), in: IEEE Micro, 24:6(74--82)

[DOI]

Buddy Threading in Distributed Applications on Simultaneous Multi-threading Processors, Nikola Vouk, Department of Computer Science, Raleigh, North California, 2005

Understanding the Overhead of the Spin-Lock Loop in CMT Architectures, Javier Verdú Vladimir Cakarevic, Petar Radojkovic and Mateo Valero, in: WIOSCA '08: In Procs. of Workshop on the Interaction between Operating Systems and Computer Architecture, 2008

Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy, Eric Tune, Rakesh Kumar, Dean M. Tullsen and Brad Calder, in: MICRO 37: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, Portland, Oregon, pages 183--194, IEEE Computer Society, 2004

[DOI]

Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor, Dean M. Tullsen, Jack L. Lo, Susan J. Eggers and Henry M. Levy, 1999

Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor, Dean M. Tullsen, Jack L. Lo, Susan J. Eggers and Henry M. Levy, in: HPCA '99: Proceedings of the IEEE 5th International Symposium on High Performance Computer Architecture, pages 54, IEEE Computer Society, 1999

Simultaneous multithreading: maximizing on-chip parallelism, Dean M. Tullsen, Susan J. Eggers and Henry M. Levy, in: ISCA '95: Proceedings of the 22th annual international symposium on Computer architecture, S. Margherita Ligure, Italy, pages 392--403, ACM Press, 1995

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Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor, Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo and Rebecca L. Stamm, in: ISCA '96: Proceedings of the 23th annual international symposium on Computer architecture, Philadelphia, Pennsylvania, United States, pages 191--202, ACM Press, 1996

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Initial Observations of the Simultaneous Multithreading Pentium 4 Processor, Nathan Tuck and Dean M. Tullsen, in: PACT '03: Proceedings of the 12th international conference on Parallel architectures and compilation techniques, pages 26, IEEE Computer Society, 2003

Exploring the Use of Hyper-Threading Technology for Multimedia Applications with Intel OpenMP Compiler, Xinmin Tian, Yen-Kuang Chen, Milind Girkar, Steven Ge, Rainer Lienhart and Sanjiv Shah, in: IPDPS '03: Proceedings of the 16th International Symposium on Parallel and Distributed Processing, pages 36.1, IEEE Computer Society, 2003

Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors, David Tam, Reza Azimi and Michael Stumm, in: EuroSys '07: Proceedings of the 2nd ACM SIGOPS/EuroSys European Conference on Computer Systems 2007, Lisbon, Portugal, pages 47--58, ACM, 2007

[DOI]

The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization, J. Greggory Steffan and Todd C. Mowry, in: HPCA '98: Proceedings of the IEEE 4th International Symposium on High Performance Computer Architecture, pages 2--13, 1998

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Characterization and analysis of HMMER and SVM-RFE parallel bioinformatics applications, E. ; Yongjian Chen; Ju Srinivasan, U.; Peng-Sheng Chen; Qian Diao; Chu-Cheow Lim; Li, in: Proceedings of the IEEE International Workload Characterization Symposium, pages 87--98, 2005

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Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors, Yonghong Song, Spiros Kalogeropulos and Partha Tirumalai, in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 99--109, IEEE Computer Society, 2005

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The Microarchitecture of Superscalar Processors, J. Smith and Gurindar S. Sohi, 1995

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Larrabee: a many-core x86 architecture for visual computing, Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan and Pat Hanrahan, in: SIGGRAPH '08: ACM SIGGRAPH 2008 papers, Los Angeles, California, pages 1--15, ACM, 2008

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Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers, Jack Sampson, Ruben Gonzalez, Jean-Francois Collard, Norman P. Jouppi, Mike Schlansker and Brad Calder, in: MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 235--246, IEEE Computer Society, 2006

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McRT-STM: a high performance software transactional memory system for a multi-core runtime, Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hudson, Chi Cao Minh and Benjamin Hertzberg, in: PPoPP '06: Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, New York, New York, USA, pages 187--197, ACM, 2006

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Evaluating the impact of simultaneous multithreading on network servers using real hardware, Yaoping Ruan, Vivek S. Pai, Erich Nahum and John M. Tracey (2005), in: SIGMETRICS Perform. Eval. Rev., 33:1(315--326)

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Dependence based prefetching for linked data structures, Amir Roth, Andreas Moshovos and Gurindar S. Sohi, in: ASPLOS-VIII: Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, United States, pages 115--126, ACM Press, 1998

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Mini-Threads: Increasing TLP on Small-Scale SMT Processors, Joshua Redstone, Susan J. Eggers and Henry Levy, in: HPCA '03: Proceedings of the IEEE 9th International Symposium on High Performance Computer Architecture, pages 19, IEEE Computer Society, 2003

Decoupled Software Pipelining with the Synchronization Array, Ram Rangan, Neil Vachharajani, Manish Vachharajani and David I. August, in: PACT '04: Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pages 177--188, IEEE Computer Society, 2004

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Compiler orchestrated prefetching via speculation and predication, Rodric M. Rabbah, Hariharan Sandanagobalane, Mongkol Ekpanyapong and Weng-Fai Wong, in: ASPLOS-XI: Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, MA, USA, pages 189--198, ACM, 2004

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Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices, Carlos Garcia Quinones, Carlos Madriles, Jesus Sanchez, Pedro Marcuello, Antonio Gonzalez and Dean M. Tullsen, in: PLDI '05: Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation, Chicago, IL, USA, pages 269--279, ACM Press, 2005

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Performance optimization of irregular codes based on the combination of reordering and blocking techniques, J. C. Pichel, D. B. Heras, J. C. Cabaleiro and F. F. Rivera (2005), in: Parallel Comput., 31:8+9(858--876)

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Simultaneous Multithreading: Present Developments and Future Directions, Miquel Pericas (2003)

A Survey of General-Purpose Computation on Graphics Hardware, John D. Owens, David Luebke, Naga Govindaraju, Mark Harris, Jens Krüger, Aaron E Lefohn and Timothy J. Purcell (2005), in: Eurographics 2005, State of the Art Reports(21--51)

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Automatic Thread Extraction with Decoupled Software Pipelining, Guilherme Ottoni, Ram Rangan, Adam Stoler and David I. August, in: MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, pages 105--118, IEEE Computer Society, 2005

Fast Synchronization on Scalable Cache-Coherent Multiprocessors using Hybrid Primitives, Dimitrios S. Nikolopoulos and D. S. Papatheodorou, in: IPDPS '00: Proceedings of the 14th International Symposium on Parallel and Distributed Processing, pages 711, IEEE Computer Society, 2000

Dynamic tiling for effective use of shared caches on multithreaded processors, Dimitrios S. Nikolopoulos (2006), in: International Journal of High Performance Computing and Networking, 2(22--35)

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Pthreads for dynamic and irregular parallelism, Girija J. Narlikar and Guy E. Blelloch, in: Supercomputing '98: Proceedings of the 1998 ACM/IEEE conference on Supercomputing, San Jose, CA, pages 1--16, IEEE Computer Society, 1998

Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling, G. S. Moshovos, A.; Sohi (2001), in: Proceedings of the IEEE, 89:11(1560--1575)

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Dynamic run-time architecture techniques for enabling continuous optimization, Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Matthew Iyer, Dan Fay, David Hodgdon, Joshua L. Kihm, Alex Settle, Dirk Grunwald and Daniel A. Connors, in: CF '05: Proceedings of the 2nd conference on Computing frontiers, Ischia, Italy, pages 211--220, ACM Press, 2005

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Methods for Modeling Resource Contention on Simultaneous Multithreading Processors, Tipp Moseley, Dirk Grunwald, Joshua L. Kihm and Daniel A. Connors, in: ICCD '05: Proceedings of the 2005 International Conference on Computer Design, pages 373--380, IEEE Computer Society, 2005

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ILP versus TLP on SMT, Nicholas Mitchell, Larry Carter, Jeanne Ferrante and Dean M. Tullsen, in: Supercomputing '99: Proceedings of the 1999 ACM/IEEE conference on Supercomputing, Portland, Oregon, United States, pages 37, ACM Press, 1999

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Algorithms for scalable synchronization on shared-memory multiprocessors, John M. Mellor-Crummey and Michael L. Scott (1995)(216--260)

Montecito: a dual-core, dual-thread Itanium processor, R. McNairy, C.; Bhatia (2005), in: IEEE Micro, 25:2(10-20)

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Hyper-Threading Technology Architecture and Microarchitecture, Deborah Marr, Frank Binns, David Hill, Glenn Hinton, David Koufaty, J. Alan Miller and Michael Upton (2002), in: Intel Technology Journal

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The Adaptive Transactional Memory Test Platform: A Tool for Experimenting with Transactional Code for Rock, Dan Nussbaum, Mark Moir and Kevin Moore, in: TRANSACT 2008: 3rd ACM SIGPLAN Workshop on Transactional Computing, 2008

Value prediction for speculative multithreaded architectures, Pedro Marcuello, Jordi Tubella and Antonio Gonzalez, in: MICRO 32: Proceedings of the 32th annual ACM/IEEE international symposium on Microarchitecture, Haifa, Israel, pages 230--236, IEEE Computer Society, 1999

Speculative multithreaded processors, Pedro Marcuello, Antonio Gonzalez and Jordi Tubella, in: ICS '98: Proceedings of the 12th annual international conference on Supercomputing, Melbourne, Australia, pages 77--84, ACM Press, 1998

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The Mitosis Speculative Multithreaded Architecture, Carlos Madriles, Carlos Garcia Quinones, Jesus Sanchez, Pedro Marcuello and Antonio Gonzalez, in: ParCo '05: Proceedings of the International Conference ParCo 2005, pages 27--38, 2005

A Study of a Simultaneous Multithreaded Processor Implementation, Dominik Madon, Eduardo Sanchez and Stefan Monnier, in: Euro-Par '99: Proceedings of the 5th International Euro-Par Conference on Parallel Processing, pages 716--726, Springer-Verlag, 1999

Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors, Chi-Keung Luk, in: ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, G\&\#246;teborg, Sweden, pages 40--51, ACM Press, 2001

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Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading, Jack L. Lo, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen and Susan J. Eggers (1997), in: ACM Trans. Comput. Syst., 15:3(322--354)

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Tuning compiler optimizations for simultaneous multithreading, Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh and Dean M. Tullsen, in: MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, Research Triangle Park, North Carolina, United States, pages 114--124, IEEE Computer Society, 1997

IBM POWER6 microarchitecture, H. Q. Le, W. J. Starke, J. S. Fields, F. P. O'Connell, D. Q. Nguyen, B. J. Ronchetti, W. M. Sauer, E. M. Schwarz and M. T. Vaden (2007), in: IBM J. Res. Dev., 51:6(639--662)

Efficient resources assignment schemes for clustered multithreaded processors, F. Latorre, J. Gonzalez and Antonio Gonzalez (2008), in: Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on(1-12)

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Exploiting the performance of 32 bit floating point arithmetic in obtaining 64 bit accuracy (revisiting iterative refinement for linear systems), Julie Langou, Julien Langou, Piotr Luszczek, Jakub Kurzak, Alfredo Buttari and Jack Dongarra, in: Supercomputing '06: Proceedings of the 2006 ACM/IEEE conference on Supercomputing, Tampa, Florida, pages 113, ACM, 2006

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A Chip-Multiprocessor Architecture with Speculative Multithreading, Venkata Krishnan and Josep Torrellas (1999), in: IEEE Trans. Comput., 48:9(866--880)

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Using Program Slicing to Drive Pre-Execution on Simultaneous Multithreading Processors, Dongkeun Kim and Donald Yeung, University of Maryland, 2001

Design and evaluation of compiler algorithms for pre-execution, Dongkeun Kim and Donald Yeung, in: ASPLOS-X: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, pages 159--170, ACM Press, 2002

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A study of source-level compiler algorithms for automatic construction of pre-execution code, Dongkeun Kim and Donald Yeung (2004), in: ACM Trans. Comput. Syst., 22:3(326--379)

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Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors, Dongkeun Kim, Steve Shih-wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar and John P. Shen, in: CGO '04: Proceedings of the International Symposium on Code Generation and Optimization, Palo Alto, California, pages 27, IEEE Computer Society, 2004

Compiler Based Pre-execution, Dongkeun Kim, 2004

The AMD Opteron processor for multiprocessor servers, K. J. ; Ahmed Keltcher, C.N.; McGrath (2003), in: IEEE Micro, 23:2(66-76)

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Lightweight lock-free synchronization methods for multithreading, Arun Kejariwal, Hideki Saito, Xinmin Tian, Milind Girkar, Wel Li, Utpal Banerjee, Alexandru Nicolau and Constantine D. Polychronopoulos, in: ICS '06: Proceedings of the 20th annual international conference on Supercomputing, Cairns, Queensland, Australia, pages 361--371, ACM, 2006

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Coarse-Grained Thread Pipelining: A Speculative Parallel Execution Model for Shared-Memory Multiprocessors, Iffat H. Kazi and David J. Lilja (2001), in: IEEE Trans. Parallel Distrib. Syst., 12:9(952--966)

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IBM Power5 chip: a dual-core multithreaded processor, J. M. Kalla, R.; Balaram Sinharoy; Tendler (2004), in: IEEE Micro, 24:2(40-47)

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Adaptive execution techniques for SMT multiprocessor architectures, Changhee Jung, Daeseob Lim, Jaejin Lee and SangYong Han, in: PPoPP '05: Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, Chicago, IL, USA, pages 236--246, ACM, 2005

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Extending OpenMP to Support Slipstream Execution Mode, Khaled Z. Ibrahim and Gregory T. Byrd, in: IPDPS '03: Proceedings of the 16th International Symposium on Parallel and Distributed Processing, pages 36.2, IEEE Computer Society, 2003

Slipstream Execution Mode for CMP-based Shared Memory Systems, Khaled Z. Ibrahim, 2003

Slipstream execution mode for CMP-based multiprocessors, K. Z. Ibrahim, Gregory T. Byrd and E. Rotenberg, in: HPCA '03: Proceedings of the IEEE 9th International Symposium on High Performance Computer Architecture, pages 179--190, 2003

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The Microarchitecture of the Pentium 4 Processor, Glenn Hinton, Dave Sager, Mike Upton, Darrell Boggs, Doug Carmean, Alan Kyker and Patrice Roussel (2001), in: inteltechnologyjournal

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Transactional Memory: Architectural Support For Lock-Free Data Structures, M. Herlihy and J. E. B. Moss, in: ISCA '93: Proceedings of the 20th annual international symposium on Computer architecture, 1993

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Transactional Memory: An Overview, Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguade, Fabrizio Gagliardi, Burton Smith and Mateo Valero, pages 8--29, IEEE Computer Society Press, 2007

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Transactional coherence and consistency: simplifying parallel hardware and software, B. D. ; Wong Hammond, L.; Carlstrom (2004), in: IEEE Micro, 24:6(92--103)

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Transactional Memory Coherence and Consistency, Lance Hammond, Vicky Wong, Mike Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis and Kunle Olukotun, in: ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture, München, Germany, pages 102, IEEE Computer Society, 2004

A Single-Chip Multiprocessor, Lance Hammond, Basem A. Nayfeh and Kunle Olukotun (1997), in: Computer, 30:9(79--85)

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Stream Programming on General-Purpose Processors, Jayanth Gummaraju and Mendel Rosenblum, in: MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, pages 343--354, IEEE Computer Society, 2005

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Exploiting coarse-grained task, data, and pipeline parallelism in stream programs, Michael I. Gordon, William Thies and Saman Amarasinghe (2006), in: SIGPLAN Not., 41:11(151--162)

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Using fine grain multithreading for energy efficient computing, Alex Gontmakher, Avi Mendelson and Assaf Schuster, in: PPoPP '07: Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming, San Jose, California, USA, pages 259--269, ACM, 2007

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A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies, Ronaldo Goncalves, Eduard Ayguade, Mateo Valero and Philippe Navaux

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Thread coloring: a scheduler proposal from user to hardware threads, Marisa Gil and Ruben Pinilla (2005), in: SIGOPS Oper. Syst. Rev., 39:2(54--70)

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Database hash-join algorithms on multithreaded computer architectures, Philip Garcia and Henry F. Korth, in: CF '06: Proceedings of the 3rd conference on Computing frontiers, Ischia, Italy, pages 241--252, ACM, 2006

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Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors, Ilya Ganusov and Martin Burtscher, in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 350--360, IEEE Computer Society, 2005

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LU-GPU: Efficient Algorithms for Solving Dense Linear Systems on Graphics Hardware, Nico Galoppo, Naga K. Govindaraju, Michael Henson and Dinesh Manocha, in: Supercomputing '05: Proceedings of the 2005 ACM/IEEE conference on Supercomputing, IEEE Computer Society, 2005

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Concurrent programming without locks, Keir Fraser and Tim Harris (2007), in: ACM Trans. Comput. Syst., 25:2(5)

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Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures, Ricardo Fernandez, Jose M. Garcia, Gregorio Bernabe and Manuel E. Acacio, in: PDP '05: Proceedings of the 13th Euromicro Conference on Parallel, Distributed and Network-Based Processing, pages 76--83, IEEE Computer Society, 2005

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Fast synchronization on shared-memory multiprocessors: an architectural approach, Zhen Fang, Lixin Zhang, John B. Carter, Liqun Cheng and Michael Parker (2005), in: J. Parallel Distrib. Comput., 65:10(1158--1170)

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Partitioning Multi-Threaded Processors with a Large Number of Threads, Ali El-Moursy, R. Garg, David H. Albonesi and S. Dwarkadas, in: ISPASS 2005: IEEE International Symposium on Performance Analysis of Systems and Software, 2005., pages 112-123, 2005

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Front-End Policies for Improved Issue Efficiency in SMT Processors, Ali El-Moursy and David H. Albonesi, in: HPCA '03: Proceedings of the 9th International Symposium on High-Performance Computer Architecture, pages 31, IEEE Computer Society, 2003

Optimizing Compiler for the CELL Processor, A. E. Eichenberger, K. O'Brien, Peng Wu, Tong Chen, P. H. Oden, D. A. Prener, J. C. Shepherd, Byoungro So, Z. Sura, A. Wang, Tao Zhang, Peng Zhao and M. Gschwind, in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 161-172, 2005

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Simultaneous Multithreading: A Platform for Next-Generation Processors, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm and Dean M. Tullsen (1997), in: IEEE Micro, 17:5(12--19)

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A Comparative study of SMT and CMP multiprocessors, Rajat A. Dua and Bhushan Lokhande

Futexes are Tricky, Ulrich Drepper (2005)

Optimizing SMT Processors for High Single-Thread Performance, Gautham K. Dorai, Donald Yeung and Seungryul Choi (2003), in: The Journal of Instruction-Level Parallelism, 5

Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance, Gautham K. Dorai and Donald Yeung, in: PACT '02: Proceedings of the 11th international conference on Parallel architectures and compilation techniques, pages 30, IEEE Computer Society, 2002

Exploiting Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors, Matthew DeVuyst, Rakesh Kumar and Dean M. Tullsen, in: IPDPS '06: Proceedings of the 20th International Symposium on Parallel and Distributed Processing, 2006

Avoiding Communication in Computing Krylov Subspaces, James W. Demmel, Mark Frederick Hoemmen, Marghoob Mohiyuddin and Katherine A. Yelick, 2007

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Transactional Locking II, Nir Shavit Dave Dice, Ori Shalev, in: DISC: Proceedings of the 20th International Symposium on Distributed Computing (DISC), Stockholm, 2006

Applications of the Adaptive Transactional Memory Test Platform, Doug Lea Dave Dice, Maurice Herlihy, in: TRANSACT 2008: 3rd ACM SIGPLAN Workshop on Transactional Computing, 2008

Integrating Multiple Forms of Multithreaded Execution on SMT Processors: A Quantitative Study with Scientific Workloads, Matthew Curtis-Maury, Tanping Wang, Christos D. Antonopoulos and Dimitrios S. Nikolopoulos, number WM-CS-2005-04, 2005

Integrating Multiple Forms of Multithreaded Execution on multi-SMT Systems: A Study with Scientific Applications, Matthew Curtis-Maury, Tanping Wang, Christos D. Antonopoulos and Dimitrios S. Nikolopoulos, in: QEST '05: Proceedings of the Second International Conference on the Quantitative Evaluation of Systems (QEST'05) on The Quantitative Evaluation of Systems, 2005

Online power-performance adaptation of multithreaded programs using hardware event-based prediction, Matthew Curtis-Maury, James Dzierwa, Christos D. Antonopoulos and Dimitrios S. Nikolopoulos, in: ICS '06: Proceedings of the 20th annual international conference on Supercomputing, Cairns, Queensland, Australia, pages 157--166, ACM, 2006

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An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors, Matthew Curtis-Maury, Xiaoning Ding, Christos D. Antonopoulos and Dimitrios S. Nikolopoulos, in: IWOMP '05: International Workshop on OpenMP, 2005

Speculative precomputation: long-range prefetching of delinquent loads, Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher Hughes, Yong-Fong Lee, Dan Lavery and John P. Shen, in: ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, G\&\#246;teborg, Sweden, pages 14--25, ACM Press, 2001

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The Common Case Transactional Behavior of Multithreaded Programs, JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom, Christos Kozyrakis and Kunle Olukotun, in: HPCA '06: Proceedings of the IEEE 12th International Symposium on High Performance Computer Architecture, 2006

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Learning-Based SMT Processor Resource Distribution via Hill-Climbing, Seungryul Choi and Donald Yeung, in: ISCA '06: Proceedings of the 33rd annual international symposium on Computer Architecture, pages 239--251, IEEE Computer Society, 2006

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Scheduling threads for constructive cache sharing on CMPs, Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry and Chris Wilkerson, in: SPAA '07: Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures, San Diego, California, USA, pages 105--115, ACM, 2007

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Simultaneous subordinate microthreading (SSMT), Robert S. Chappell, Jared Stark, Sangwook P. Kim, Steven K. Reinhardt and Yale N. Patt (1999), in: ISCA '99: Proceedings of the 26th annual international symposium on Computer architecture:2(186--195)

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Dynamically Controlled Resource Allocation in SMT Processors, Francisco J. Cazorla, Alex Ramirez, Mateo Valero and Enrique Fernandez, in: MICRO 37: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, Portland, Oregon, pages 171--182, IEEE Computer Society, 2004

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Predictable performance in SMT processors, Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero, in: CF '04: Proceedings of the 1st conference on Computing frontiers, Ischia, Italy, pages 433--443, ACM Press, 2004

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An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees, Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Bronson, Jared Casper, Christos Kozyrakis and Kunle Olukotun, in: ISCA '07: Proceedings of the 34th Annual International Symposium on Computer Architecture, 2007

Hyper-Threading Aware Process Scheduling Heuristics, James R. Bulpin and Ian A. Pratt, in: ATEC'05: Proceedings of the USENIX Annual Technical Conference 2005 on USENIX Annual Technical Conference, Anaheim, CA, pages 27--27, USENIX Association, 2005

Operating system support for simultaneous multithreaded processors, James R. Bulpin, 2005

Speculative Precomputation on Chip Multiprocessors, Jeffery A. Brown, Hong Wang, George Chrysos, Perry H. Wang and John P. Shen, in: MTEAC-6 : 6th Workshop on Multithreaded Execution, Architecture, and Compilation, 2002

The shared-thread multiprocessor, Jeffery A. Brown and Dean M. Tullsen, in: ICS '08: Proceedings of the 22nd annual international conference on Supercomputing, Island of Kos, Greece, pages 73--82, ACM, 2008

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Software-Controlled Priority Characterization of POWER5 Processor, Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher and Mateo Valero (2008), in: SIGARCH Comput. Archit. News, 36:3(415--426)

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The M5 Simulator: Modeling Networked Systems, Nathan L. Binkert, Ronald G. Dreslinski, Lisa R. Hsu, Kevin T. Lim, Ali G. Saidi and Steven K. Reinhardt (2006), in: IEEE Micro, 26:4(52--60)

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A General Compiler Framework for Speculative Multithreaded Processors., Anasua Bhowmik and Manoj Franklin (2004), in: IEEE Trans. Parallel Distrib. Syst., 15:8(713--724)

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The OpenTM Transactional Application Programming Interface, Woongki Baek, Chi Cao Minh, Martin Trautmann, Christos Kozyrakis and Kunle Olukotun, in: PACT '07: Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques, pages 376--387, IEEE Computer Society, 2007

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Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture, Subhradyuti Sarkar and Dean M. Tullsen, in: HiPEAC, pages 353-368, 2008

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Thread-Spawning Schemes for Speculative Multithreading, Pedro Marcuello and Antonio Gonzalez, in: HPCA '02: Proceedings of the IEEE 8th International Symposium on High Performance Computer Architecture, pages 55, IEEE Computer Society, 2002

The Landscape of Parallel Computing Research: A View from Berkeley, K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, Parry Husbands, K. Keutzer, David Patterson, W. L. Plishker, John Shalf, Samuel Williams and Katherine A. Yelick, EECS Department, University of California, Berkeley, number UCB/EECS-2006-183, 2006

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Multigrain parallel Delaunay Mesh generation: challenges and opportunities for multithreaded architectures, Christos D. Antonopoulos, Xiaoning Ding, Andrey Chernikov, Filip Blagojevic, Dimitrios S. Nikolopoulos and Nikos Chrisochoides, in: ICS '05: Proceedings of the 19th annual international conference on Supercomputing, Cambridge, Massachusetts, pages 367--376, ACM, 2005

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The Tera computer system, Robert Alverson, David Callahan, Daniel Cummings, Brian Koblenz, Allan Porterfield and Burton Smith, in: ICS '90: Proceedings of the 4th international conference on Supercomputing, Amsterdam, The Netherlands, pages 1--6, ACM, 1990

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Unlocking concurrency, Ali-Reza Adl-Tabatabai, Christos Kozyrakis and Bratin Saha (2007), in: Queue, 4:10(24--33)

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Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs., Yun Zhang and Michael Voss, in: IPDPS '05: Proceedings of the 19th International Symposium on Parallel and Distributed Processing, 2005

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smt- SPRINTS: Software Precomputation with Intelligent Streaming for Resource-Constrained SMTs., Tanping Wang, Christos D. Antonopoulos and Dimitrios S. Nikolopoulos, in: Euro-Par '05: Proceedings of the 11th International Euro-Par Conference on Parallel Processing, pages 710--719, 2005

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A Minimal Dual-Core Speculative Multi-Threading Architecture., Srikanth T. Srinivasan, Haitham Akkary, Tom Holman and Konrad Lai, in: ICCD '04: Proceedings of the 2004 International Conference on Computer Design, pages 360--367, 2004

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Architectural Support for Enhanced SMT Job Scheduling., Alex Settle, Joshua L. Kihm, Andrew Janiszewski and Daniel A. Connors, in: PACT '04: Proceedings of the 13th international conference on Parallel architectures and compilation techniques, pages 63--73, 2004

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Code and Data Transformations for Improving Shared Cache Performance on SMT Processors., Dimitrios S. Nikolopoulos, in: ISHPC, pages 54--69, 2003

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Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors., Robert L. McGregor, Christos D. Antonopoulos and Dimitrios S. Nikolopoulos, in: IPDPS '05: Proceedings of the 19th International Symposium on Parallel and Distributed Processing, 2005

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Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling., Joshua L. Kihm and Daniel A. Connors, in: ICCD '04: Proceedings of the 2004 International Conference on Computer Design, pages 326--331, 2004

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