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All publications sorted by title
A
| A Chip-Multiprocessor Architecture with Speculative Multithreading, and (1999), in: IEEE Trans. Comput., 48:9(866--880) |
[DOI] |
| A data locality optimizing algorithm, and , in: PLDI '91: Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, Toronto, Ontario, Canada, pages 30--44, ACM, 1991 |
[DOI] |
| A fast, parallel spanning tree algorithm for symmetric multiprocessors (SMPs), and (2005), in: J. Parallel Distrib. Comput., 65:9(994--1006) |
[DOI] |
| A General Compiler Framework for Speculative Multithreaded Processors., and (2004), in: IEEE Trans. Parallel Distrib. Syst., 15:8(713--724) |
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| A general framework for prefetch scheduling in linked data structures and its application to multi-chain prefetching, , , , and (2004), in: ACM Trans. Comput. Syst., 22:2(214--280) |
[DOI] |
| A Minimal Dual-Core Speculative Multi-Threading Architecture., , , and , in: ICCD '04: Proceedings of the 2004 International Conference on Computer Design, pages 360--367, 2004 |
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| A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning, , and , in: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), pages 117-, 2002 |
| A Parallelization of Dijkstra's Shortest Path Algorithm, , , and , in: MFCS '98: Proceedings of the 23rd International Symposium on Mathematical Foundations of Computer Science, pages 722--731, Springer-Verlag, 1998 |
| A Prefetching Technique for Irregular Accesses to Linked Data Structures, , and , in: HPCA '00: Proceedings of the IEEE 6th International Symposium on High Performance Computer Architecture, pages 206--217, 2000 |
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| A quantitative framework for automated pre-execution thread selection, and , in: MICRO 35: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, Istanbul, Turkey, pages 430--441, IEEE Computer Society Press, 2002 |
| A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework, , and , in: CGO '06: Proceedings of the International Symposium on Code Generation and Optimization, pages 50--64, IEEE Computer Society, 2006 |
[DOI] |
| A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies, , , and |
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| A Single-Chip Multiprocessor, , and (1997), in: Computer, 30:9(79--85) |
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| A Smart HPC Interconnect for Clusters of Virtual Machines, , , , and , in: 6th Workshop on Virtualization in High-Performance Cloud Computing (VHPC '11), 2011 |
| A Study of a Simultaneous Multithreaded Processor Implementation, , and , in: Euro-Par '99: Proceedings of the 5th International Euro-Par Conference on Parallel Processing, pages 716--726, Springer-Verlag, 1999 |
| A Study of a Transactional Parallel Routing Algorithm, , and , in: PACT '07: Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques, pages 388--398, IEEE Computer Society, 2007 |
[DOI] |
| A study of source-level compiler algorithms for automatic construction of pre-execution code, and (2004), in: ACM Trans. Comput. Syst., 22:3(326--379) |
[DOI] |
| A Survey of General-Purpose Computation on Graphics Hardware, , , , , , and (2005), in: Eurographics 2005, State of the Art Reports(21--51) |
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| A Survey of Packages for Large Linear Systems, and |
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| A Technique for Variable Dependence Driven Loop Peeling, and , in: ICA3PP '02: Proceedings of the Fifth International Conference on Algorithms and Architectures for Parallel Processing, pages 390, IEEE Computer Society, 2002 |
| Accelerating and Adapting Precomputation Threads for Effcient Prefetching, , and , in: HPCA '07: Proceedings of the IEEE 13th International Symposium on High Performance Computer Architecture, pages 85--95, IEEE Computer Society, 2007 |
[DOI] |
| Achieving 10 Gb/s using safe and transparent network interface virtualization, , , , and , in: VEE '09: Proceedings of the 2009 ACM SIGPLAN/SIGOPS international conference on Virtual execution environments, Washington, DC, USA, pages 61--70, ACM, 2009 |
[DOI] |
| Adaptive execution techniques for SMT multiprocessor architectures, , , and , in: PPoPP '05: Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, Chicago, IL, USA, pages 236--246, ACM, 2005 |
[DOI] |
| Algorithms for scalable synchronization on shared-memory multiprocessors, and (1995)(216--260) |
| An Adaptive OpenMP Loop Scheduler for Hyperthreaded SMPs, , , , and , in: PDCS '04, 2004 |
| An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees, , , , , , , and , in: ISCA '07: Proceedings of the 34th Annual International Symposium on Computer Architecture, 2007 |
| An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors, , , and , in: IWOMP '05: International Workshop on OpenMP, 2005 |
| An Experimental Study of A Parallel Shortest Path Algorithm for Solving Large-Scale Graph Instances, , , and (2007) |
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| An Implementation and Analysis of the Virtual Interface Architecture, , and , in: Supercomputing, 1998. SC98. IEEE/ACM Conference on, pages 16 - 16, 1998 |
[DOI] |
| An RDMA Protocol Specification (Version 1.0) This document is a Release Specification of the RDMA Consortium., , , and , 2002 |
| Analysis of Memory Behavior of DIS Stressmark Suite and Optimization, , 2000 |
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| Applications of the Adaptive Transactional Memory Test Platform, , in: TRANSACT 2008: 3rd ACM SIGPLAN Workshop on Transactional Computing, 2008 |
| Architectural Support for Enhanced SMT Job Scheduling., , , and , in: PACT '04: Proceedings of the 13th international conference on Parallel architectures and compilation techniques, pages 63--73, 2004 |
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| Architectural support for user-level network interfaces in heavily virtualized systems, and , in: WIOV'10: Proceedings of the 2nd conference on I/O virtualization, Pittsburgh, PA, USA, pages 7--7, USENIX, 2010 |
| Automatic Compiler-Inserted Prefetching for Pointer-Based Applications, and (1999), in: IEEE Trans. Comput., 48:2(134--141) |
[DOI] |
| Automatic Thread Extraction with Decoupled Software Pipelining, , , and , in: MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, pages 105--118, IEEE Computer Society, 2005 |
| Avoiding Communication in Computing Krylov Subspaces, , , and , 2007 |
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B
| Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy, , , and , in: MICRO 37: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, Portland, Oregon, pages 183--194, IEEE Computer Society, 2004 |
[DOI] |
| Basic Local Alignment Search Tool, , , , and (1990), in: Journal of Molecular Biology, 215:3(403--410) |
| Benchmarking Amazon EC2 for high-performance scientific computing, (2008), in: LOGIN, 33:5(18--23) |
| Beyond server consolidation, (2008), in: Queue, 6:1(20--26) |
| Borrowed-Virtual-Time (BVT) scheduling: supporting latency-sensitive threads in a general-purpose scheduler, (1999), in: ACM, 33(261-276) |
| Breaking up is hard to do: security and functionality in a commodity hypervisor, , , , , , , and , in: Proceedings of the Twenty-Third ACM Symposium on Operating Systems Principles, Cascais, Portugal, pages 189--202, ACM, 2011 |
[DOI] |
| Bridging the gap between software and hardware techniques for I/O virtualization, , , and , in: ATC'08: USENIX 2008 Annual Technical Conference on Annual Technical Conference, Boston, Massachusetts, pages 29--42, USENIX, 2008 |
| Buddy Threading in Distributed Applications on Simultaneous Multi-threading Processors, , Department of Computer Science, Raleigh, North California, 2005 |
C
| Characterization and analysis of HMMER and SVM-RFE parallel bioinformatics applications, , in: Proceedings of the IEEE International Workload Characterization Symposium, pages 87--98, 2005 |
[DOI] |
| CIEL: a universal execution engine for distributed data-flow computing, , , , , and , in: Proceedings of the 8th USENIX conference on Networked systems design and implementation, Boston, MA, pages 9--9, USENIX Association, 2011 |
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| Cilk: An Efficient Multithreaded Runtime System, , , , , and (1996), in: Journal of Parallel and Distributed Computing, 37:1(55--69) |
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| Coarse-Grained Thread Pipelining: A Speculative Parallel Execution Model for Shared-Memory Multiprocessors, and (2001), in: IEEE Trans. Parallel Distrib. Syst., 12:9(952--966) |
[DOI] |
| Code and Data Transformations for Improving Shared Cache Performance on SMT Processors., , in: ISHPC, pages 54--69, 2003 |
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| Coexisting Scheduling Policies Boosting I/O Virtual Machines, , and , in: Euro-Par 2011: Parallel Processing Workshops, pages 407-415, Springer Berlin Heidelberg, 2012 |
[DOI] |
| Coming challenges in microarchitecture and architecture, , , , , and , 2001 |
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| Compiler Based Pre-execution, , 2004 |
| Compiler orchestrated prefetching via speculation and predication, , , and , in: ASPLOS-XI: Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, MA, USA, pages 189--198, ACM, 2004 |
[DOI] |
| Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture, and , in: HiPEAC, pages 353-368, 2008 |
[DOI] |
| Compiler-Based Prefetching for Recursive Data Structures, and , in: ASPLOS-VII: Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 222--233, 1996 |
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| Computer Architecture. A Quantitative Approach, and , pages 373-504, Morgan Kaufmann Pub., 2002 |
| Concurrent Direct Network Access for Virtual Machine Monitors, , , , , , and , in: HPCA '07: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pages 306--317, IEEE Computer Society, 2007 |
| Concurrent programming without locks, and (2007), in: ACM Trans. Comput. Syst., 25:2(5) |
[DOI] |
| Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading, , , , , and (1997), in: ACM Trans. Comput. Syst., 15:3(322--354) |
[DOI] |
D
| Database hash-join algorithms on multithreaded computer architectures, and , in: CF '06: Proceedings of the 3rd conference on Computing frontiers, Ischia, Italy, pages 241--252, ACM, 2006 |
[DOI] |
| Decoupled Software Pipelining with the Synchronization Array, , , and , in: PACT '04: Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pages 177--188, IEEE Computer Society, 2004 |
[DOI] |
| Delta-stepping: A parallel single source shortest path algorithm, , in: In ESA ?98: Proceedings of the 6th Annual European Symposium on Algorithms, pages 393--404, Springer-Verlag, 1998 |
| Denali: Lightweight Virtual Machines for Distributed and Networked Applications, , and , in: In Proc. of the USENIX Annual Technical Conference, 2002 |
| Dependence based prefetching for linked data structures, , and , in: ASPLOS-VIII: Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, United States, pages 115--126, ACM Press, 1998 |
[DOI] |
| Design and evaluation of a compiler algorithm for prefetching, , and (1992), in: SIGPLAN Not., 27:9(62--73) |
[DOI] |
| Design and evaluation of compiler algorithms for pre-execution, and , in: ASPLOS-X: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, pages 159--170, ACM Press, 2002 |
[DOI] |
| Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors, , and , in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 99--109, IEEE Computer Society, 2005 |
[DOI] |
| Design and Implementation of Open-MX: High-Performance Message Passing over generic Ethernet hardware, , in: CAC 2008: Workshop on Communication Architecture for Clusters, held in conjunction with IPDPS 2008, IEEE Computer Society Press, 2008 |
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| Design and Implementation of the HPCS Graph Analysis Benchmark on Symmetric Multiprocessors, and (2005), in: High Performance Computing ? HiPC 2005, 3769(465-476) |
| Designing Multithreaded Algorithms for Breadth-First Search and st-connectivity on the Cray MTA-2, and , in: ICPP '06: Proceedings of the 2006 International Conference on Parallel Processing, pages 523--530, IEEE Computer Society, 2006 |
[DOI] |
| Device Driver Safety Through a Reference Validation Mechanism, , , , and , in: 8th Symposium on Operating Systems Design and Implementation (OSDI), San Diego, Dec 2008, 2008 |
| Direct Device Assignment for Untrusted Fully-Virtualized Virtual Machines, , and , IBM Research, number H-0263, Technical Report, 2008 |
| Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window, , in: PACT '05: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, pages 231--242, IEEE Computer Society, 2005 |
[DOI] |
| Dynamic run-time architecture techniques for enabling continuous optimization, , , , , , , , , and , in: CF '05: Proceedings of the 2nd conference on Computing frontiers, Ischia, Italy, pages 211--220, ACM Press, 2005 |
[DOI] |
| Dynamic tiling for effective use of shared caches on multithreaded processors, (2006), in: International Journal of High Performance Computing and Networking, 2(22--35) |
[DOI] |
| Dynamically Controlled Resource Allocation in SMT Processors, , , and , in: MICRO 37: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, Portland, Oregon, pages 171--182, IEEE Computer Society, 2004 |
[DOI] |
E
| Effects of Memory Performance on Parallel Job Scheduling, , and (2001), in: Lecture Notes in Computer Science, 2221(116-) |
| Efficient resources assignment schemes for clustered multithreaded processors, , and (2008), in: Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on(1-12) |
[DOI] |
| Efficient shared memory message passing for inter-VM communications, , , and , in: 4th Workshop on Virtualization in High-Performance Cloud Computing (VHPC '08), Euro-par 2008, 2008 |
| Efficient Virtualization of High-Performance Network Interfaces, , and , in: ICN '09: Proceedings of the 2009 Eighth International Conference on Networks, pages 434--439, IEEE Computer Society, 2009 |
[DOI] |
| ELI: Bare-Metal Performance for I/O Virtualization, , , , , , and , in: ACM Architectural Support for Programming Languages \& Operating Systems (ASPLOS), 2012 |
| Essential Linux Device Drivers, (2008):TR-0168(231--244) |
| Evaluating the Impact of RDMA on Storage I/O over InfiniBand, , , and , in: SAN-03 Work- shop (in conjunction with HPCA), 2004, 2004 |
| Evaluating the impact of simultaneous multithreading on network servers using real hardware, , , and (2005), in: SIGMETRICS Perform. Eval. Rev., 33:1(315--326) |
[DOI] |
| Evaluating the Performance Impact of Xen on MPI and Process Execution For HPC Systems, , , and , in: 1st Intern. Workshop on Virtualization Techn. in Dstrb. Computing. VTDC 2006., 2006 |
[DOI] |
| Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors, , and (1995), in: Journal of Parallel and Distributed Computing, 24:2(139--151) |
| Execution-based prediction using speculative slices, and , in: ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, G\&\#246;teborg, Sweden, pages 2--13, ACM Press, 2001 |
[DOI] |
| Exploiting Application-Level Information to Reduce Memory Bandwidth Consumption, and , in: Proceedings of the 4th Workshop on Complexity-Effective Design, held in conjunction with the 30th International Symposium on Computer Architecture (ISCA-30), 2003 |
| Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor, , , , , and , in: ISCA '96: Proceedings of the 23th annual international symposium on Computer architecture, Philadelphia, Pennsylvania, United States, pages 191--202, ACM Press, 1996 |
[DOI] |
| Exploiting coarse-grained task, data, and pipeline parallelism in stream programs, , and (2006), in: SIGPLAN Not., 41:11(151--162) |
[DOI] |
| Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers, , , , , and , in: MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 235--246, IEEE Computer Society, 2006 |
[DOI] |
| Exploiting Speculative Thread-Level Parallelism on a SMT Processor, and , in: HPCN, pages 754--763, Springer-Verlag, 1999 |
| Exploiting the performance of 32 bit floating point arithmetic in obtaining 64 bit accuracy (revisiting iterative refinement for linear systems), , , , , and , in: Supercomputing '06: Proceedings of the 2006 ACM/IEEE conference on Supercomputing, Tampa, Florida, pages 113, ACM, 2006 |
[DOI] |
| Exploiting Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors, , and , in: IPDPS '06: Proceedings of the 20th International Symposium on Parallel and Distributed Processing, 2006 |
| Exploring I/O Virtualization Data paths for MPI Applications in a Cluster of VMs: A Networking Perspective, , and , in: 5th Workshop on Virtualization in High-Performance Cloud Computing (VHPC '10), 2010 |
| Exploring the Use of Hyper-Threading Technology for Multimedia Applications with Intel OpenMP Compiler, , , , , and , in: IPDPS '03: Proceedings of the 16th International Symposium on Parallel and Distributed Processing, pages 36.1, IEEE Computer Society, 2003 |
| Extending OpenMP to Support Slipstream Execution Mode, and , in: IPDPS '03: Proceedings of the 16th International Symposium on Parallel and Distributed Processing, pages 36.2, IEEE Computer Society, 2003 |
| Extending the OpenMP Standard for Thread Mapping and Grouping, , in: IWOMP '06: International Workshop on OpenMP, 2006 |
F
| Fast Synchronization on Scalable Cache-Coherent Multiprocessors using Hybrid Primitives, and , in: IPDPS '00: Proceedings of the 14th International Symposium on Parallel and Distributed Processing, pages 711, IEEE Computer Society, 2000 |
| Fast synchronization on shared-memory multiprocessors: an architectural approach, , , , and (2005), in: J. Parallel Distrib. Comput., 65:10(1158--1170) |
[DOI] |
| Formal Requirements for Virtualizable Third Generation Architectures, (1974), in: ACM, 17(412-421) |
| Front-End Policies for Improved Issue Efficiency in SMT Processors, and , in: HPCA '03: Proceedings of the 9th International Symposium on High-Performance Computer Architecture, pages 31, IEEE Computer Society, 2003 |
| Futexes are Tricky, (2005) |
| Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors, and , in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 350--360, IEEE Computer Society, 2005 |
[DOI] |
G
| Gang Scheduling Performance Benefits for Fine-Grain Synchronization, and (1992), in: Journal of Parallel and Distributed Computing, 16:4(306--318) |
| Gang Scheduling with Memory Considerations, and , in: Proceedings of the 14th International Parallel and Distributed Processing Symposium (IPDPS 2000), pages 109--114, 2000 |
| Getting 10 Gb/s from Xen: Safe and Fast Device Access from Unprivileged Domains, , in: Euro-Par 2007 Workshops: Parallel Processing, 2007 |
| GM: A Message-Passing System for Myrinet Networks, , 2003 |
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| GMBlock: Optimizing data movement in a block-level storage sharing system over Myrinet, , and (2010), in: Cluster Computing, 13(349-372) |
[DOI] |
| GNBD/VIA: a network block device over virtual interface architecture on Linux, , and , in: Parallel and Distributed Processing Symposium., Proceedings International, IPDPS 2002, Abstracts and CD-ROM, pages 7 pp-, 2002 |
[DOI] |
| GPUfs: Integrating a File System with GPUs, , , and , in: Proceedings of the Eighteenth International Conference on Architectural Support for Programming Languages and Operating Systems, Houston, Texas, USA, pages 485--498, ACM, 2013 |
[DOI] |
H
| Handling long-latency loads in a simultaneous multithreading processor, and , in: MICRO 34: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, Austin, Texas, pages 318--327, IEEE Computer Society, 2001 |
| Helper threads via virtual multithreading, , , , , , , , , and (2004), in: IEEE Micro, 24:6(74--82) |
[DOI] |
| Helper threads via virtual multithreading on an experimental itanium2 processor-based platform, , , , , , , , , and (2004), in: SIGOPS Oper. Syst. Rev., 38:5(144--155) |
[DOI] |
| High performance and scalable I/O virtualization via self-virtualized devices, and , in: HPDC '07: Proceedings of the 16th international symposium on High performance distributed computing, Monterey, California, USA, pages 179--188, ACM, 2007 |
[DOI] |
| High performance and scalable I/O virtualization via self-virtualized devices, and , in: HPDC '07: Proceedings of the 16th international symposium on High performance distributed computing, Monterey, California, USA, pages 179--188, ACM, 2007 |
[DOI] |
| High Performance Block I/O for Global File System (GFS) with InfiniBand RDMA, , and , in: Parallel Processing, 2006. ICPP 2006. International Conference on, pages 391-398, 2006 |
[DOI] |
| High Performance Virtual Machine Migration with RDMA over Modern Interconnects., , , and , in: EEE International Conference on Cluster Computing (Cluster'07), Austin, TX, 2007 |
| High performance VMM-bypass I/O in virtual machines, , , and , in: ATEC '06: Proceedings of the annual conference on USENIX '06 Annual Technical Conference, Boston, MA, pages 3--3, USENIX, 2006 |
| High performance VMM-bypass I/O in virtual machines, (2006), in: ATEC |
| High-Performance Message Passing over generic Ethernet Hardware with Open-MX, (2011), in: Parallel Computing, 37:2(85-100) |
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| Hitting the Memory Wall: Implications of the Obvious, and (1995), in: ACM SIGARCH Computer Architecture News, 23:1(20--24) |
| Hyper-Threading Aware Process Scheduling Heuristics, and , in: ATEC'05: Proceedings of the USENIX Annual Technical Conference 2005 on USENIX Annual Technical Conference, Anaheim, CA, pages 27--27, USENIX Association, 2005 |
| Hyper-Threading Technology Architecture and Microarchitecture, , , , , , and (2002), in: Intel Technology Journal |
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I
| IA-32 Intel Architecture Optimization Reference Manual, Intel Corporation |
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| IBM Power5 chip: a dual-core multithreaded processor, (2004), in: IEEE Micro, 24:2(40-47) |
[DOI] |
| IBM POWER6 microarchitecture, , , , , , , , and (2007), in: IBM J. Res. Dev., 51:6(639--662) |
| IEEE Standard for Scalable Coherent Interface (SCI), , Standard 1596-1992, 1992 |
| ILP versus TLP on SMT, , , and , in: Supercomputing '99: Proceedings of the 1999 ACM/IEEE conference on Supercomputing, Portland, Oregon, United States, pages 37, ACM Press, 1999 |
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| Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling., and , in: ICCD '04: Proceedings of the 2004 International Conference on Computer Design, pages 326--331, 2004 |
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