Computer Architecture
Topic: --to be processed
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Publications for topic "--to be processed" sorted by recency
| Omni OpenMP Compiler Project, Released in the International Conference for High Performance Computing, Networking and Storage (SC'03), 2003 |
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| Accelerating and Adapting Precomputation Threads for Effcient Prefetching, , and , in: HPCA '07: Proceedings of the IEEE 13th International Symposium on High Performance Computer Architecture, pages 85--95, IEEE Computer Society, 2007 |
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| Runtime support for integrating precomputation and thread-level parallelism on simultaneous multithreaded processors, , and , in: LCR '04: Proceedings of the 7th workshop on Workshop on languages, compilers, and run-time support for scalable systems, Houston, Texas, pages 1--12, ACM Press, 2004 |
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| Initial Observations of the Simultaneous Multithreading Pentium 4 Processor, and , in: PACT '03: Proceedings of the 12th international conference on Parallel architectures and compilation techniques, pages 26, IEEE Computer Society, 2003 |
| The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization, and , in: HPCA '98: Proceedings of the IEEE 4th International Symposium on High Performance Computer Architecture, pages 2--13, 1998 |
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| Characterization and analysis of HMMER and SVM-RFE parallel bioinformatics applications, , in: Proceedings of the IEEE International Workload Characterization Symposium, pages 87--98, 2005 |
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| Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors, , and , in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 99--109, IEEE Computer Society, 2005 |
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| Evaluating the impact of simultaneous multithreading on network servers using real hardware, , , and (2005), in: SIGMETRICS Perform. Eval. Rev., 33:1(315--326) |
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| Dependence based prefetching for linked data structures, , and , in: ASPLOS-VIII: Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, United States, pages 115--126, ACM Press, 1998 |
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| Mini-Threads: Increasing TLP on Small-Scale SMT Processors, , and , in: HPCA '03: Proceedings of the IEEE 9th International Symposium on High Performance Computer Architecture, pages 19, IEEE Computer Society, 2003 |
| Compiler orchestrated prefetching via speculation and predication, , , and , in: ASPLOS-XI: Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, MA, USA, pages 189--198, ACM, 2004 |
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| Performance optimization of irregular codes based on the combination of reordering and blocking techniques, , , and (2005), in: Parallel Comput., 31:8+9(858--876) |
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| Automatic Thread Extraction with Decoupled Software Pipelining, , , and , in: MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, pages 105--118, IEEE Computer Society, 2005 |
| Pthreads for dynamic and irregular parallelism, and , in: Supercomputing '98: Proceedings of the 1998 ACM/IEEE conference on Supercomputing, San Jose, CA, pages 1--16, IEEE Computer Society, 1998 |
| Dynamic run-time architecture techniques for enabling continuous optimization, , , , , , , , , and , in: CF '05: Proceedings of the 2nd conference on Computing frontiers, Ischia, Italy, pages 211--220, ACM Press, 2005 |
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| Exploiting the performance of 32 bit floating point arithmetic in obtaining 64 bit accuracy (revisiting iterative refinement for linear systems), , , , , and , in: Supercomputing '06: Proceedings of the 2006 ACM/IEEE conference on Supercomputing, Tampa, Florida, pages 113, ACM, 2006 |
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| Coarse-Grained Thread Pipelining: A Speculative Parallel Execution Model for Shared-Memory Multiprocessors, and (2001), in: IEEE Trans. Parallel Distrib. Syst., 12:9(952--966) |
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| Exploiting coarse-grained task, data, and pipeline parallelism in stream programs, , and (2006), in: SIGPLAN Not., 41:11(151--162) |
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| Using fine grain multithreading for energy efficient computing, , and , in: PPoPP '07: Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming, San Jose, California, USA, pages 259--269, ACM, 2007 |
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| Thread coloring: a scheduler proposal from user to hardware threads, and (2005), in: SIGOPS Oper. Syst. Rev., 39:2(54--70) |
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| Concurrent programming without locks, and (2007), in: ACM Trans. Comput. Syst., 25:2(5) |
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| Partitioning Multi-Threaded Processors with a Large Number of Threads, , , and , in: ISPASS 2005: IEEE International Symposium on Performance Analysis of Systems and Software, 2005., pages 112-123, 2005 |
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| Optimizing SMT Processors for High Single-Thread Performance, , and (2003), in: The Journal of Instruction-Level Parallelism, 5 |
| Avoiding Communication in Computing Krylov Subspaces, , , and , 2007 |
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| Online power-performance adaptation of multithreaded programs using hardware event-based prediction, , , and , in: ICS '06: Proceedings of the 20th annual international conference on Supercomputing, Cairns, Queensland, Australia, pages 157--166, ACM, 2006 |
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| Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture, and , in: HiPEAC, pages 353-368, 2008 |
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| The Landscape of Parallel Computing Research: A View from Berkeley, , , , , , , , , , and , EECS Department, University of California, Berkeley, number UCB/EECS-2006-183, 2006 |
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