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Topic: Computer Architecture
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Publications for topic "Computer Architecture" sorted by first author
| Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations (2006), in: IEEE Trans. Comput., 55:3(268--280) |
[DOI] |
| Omni OpenMP Compiler Project, Released in the International Conference for High Performance Computing, Networking and Storage (SC'03), 2003 |
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A
| Unlocking concurrency, , and (2007), in: Queue, 4:10(24--33) |
[DOI] |
| The Tera computer system, , , , , and , in: ICS '90: Proceedings of the 4th international conference on Supercomputing, Amsterdam, The Netherlands, pages 1--6, ACM, 1990 |
[DOI] |
| Multigrain parallel Delaunay Mesh generation: challenges and opportunities for multithreaded architectures, , , , , and , in: ICS '05: Proceedings of the 19th annual international conference on Supercomputing, Cambridge, Massachusetts, pages 367--376, ACM, 2005 |
[DOI] |
| The Landscape of Parallel Computing Research: A View from Berkeley, , , , , , , , , , and , EECS Department, University of California, Berkeley, number UCB/EECS-2006-183, 2006 |
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B
| The OpenTM Transactional Application Programming Interface, , , , and , in: PACT '07: Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques, pages 376--387, IEEE Computer Society, 2007 |
[DOI] |
| A General Compiler Framework for Speculative Multithreaded Processors., and (2004), in: IEEE Trans. Parallel Distrib. Syst., 15:8(713--724) |
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| The M5 Simulator: Modeling Networked Systems, , , , , and (2006), in: IEEE Micro, 26:4(52--60) |
[DOI] |
| Software-Controlled Priority Characterization of POWER5 Processor, , , , , and (2008), in: SIGARCH Comput. Archit. News, 36:3(415--426) |
[DOI] |
| The shared-thread multiprocessor, and , in: ICS '08: Proceedings of the 22nd annual international conference on Supercomputing, Island of Kos, Greece, pages 73--82, ACM, 2008 |
[DOI] |
| Speculative Precomputation on Chip Multiprocessors, , , , and , in: MTEAC-6 : 6th Workshop on Multithreaded Execution, Architecture, and Compilation, 2002 |
| Hyper-Threading Aware Process Scheduling Heuristics, and , in: ATEC'05: Proceedings of the USENIX Annual Technical Conference 2005 on USENIX Annual Technical Conference, Anaheim, CA, pages 27--27, USENIX Association, 2005 |
C
| An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees, , , , , , , and , in: ISCA '07: Proceedings of the 34th Annual International Symposium on Computer Architecture, 2007 |
| Predictable performance in SMT processors, , , , , and , in: CF '04: Proceedings of the 1st conference on Computing frontiers, Ischia, Italy, pages 433--443, ACM Press, 2004 |
[DOI] |
| Dynamically Controlled Resource Allocation in SMT Processors, , , and , in: MICRO 37: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, Portland, Oregon, pages 171--182, IEEE Computer Society, 2004 |
[DOI] |
| Simultaneous subordinate microthreading (SSMT), , , , and (1999), in: ISCA '99: Proceedings of the 26th annual international symposium on Computer architecture:2(186--195) |
[DOI] |
| Scheduling threads for constructive cache sharing on CMPs, , , , , , , , , , and , in: SPAA '07: Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures, San Diego, California, USA, pages 105--115, ACM, 2007 |
[DOI] |
| Learning-Based SMT Processor Resource Distribution via Hill-Climbing, and , in: ISCA '06: Proceedings of the 33rd annual international symposium on Computer Architecture, pages 239--251, IEEE Computer Society, 2006 |
[DOI] |
| The Common Case Transactional Behavior of Multithreaded Programs, , , , , , and , in: HPCA '06: Proceedings of the IEEE 12th International Symposium on High Performance Computer Architecture, 2006 |
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| Speculative precomputation: long-range prefetching of delinquent loads, , , , , , and , in: ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, G\&\#246;teborg, Sweden, pages 14--25, ACM Press, 2001 |
[DOI] |
| An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors, , , and , in: IWOMP '05: International Workshop on OpenMP, 2005 |
| Online power-performance adaptation of multithreaded programs using hardware event-based prediction, , , and , in: ICS '06: Proceedings of the 20th annual international conference on Supercomputing, Cairns, Queensland, Australia, pages 157--166, ACM, 2006 |
[DOI] |
| Integrating Multiple Forms of Multithreaded Execution on multi-SMT Systems: A Study with Scientific Applications, , , and , in: QEST '05: Proceedings of the Second International Conference on the Quantitative Evaluation of Systems (QEST'05) on The Quantitative Evaluation of Systems, 2005 |
| Integrating Multiple Forms of Multithreaded Execution on SMT Processors: A Quantitative Study with Scientific Workloads, , , and , number WM-CS-2005-04, 2005 |
D
| Applications of the Adaptive Transactional Memory Test Platform, , in: TRANSACT 2008: 3rd ACM SIGPLAN Workshop on Transactional Computing, 2008 |
| Transactional Locking II, , in: DISC: Proceedings of the 20th International Symposium on Distributed Computing (DISC), Stockholm, 2006 |
| Avoiding Communication in Computing Krylov Subspaces, , , and , 2007 |
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| Exploiting Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors, , and , in: IPDPS '06: Proceedings of the 20th International Symposium on Parallel and Distributed Processing, 2006 |
| Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance, and , in: PACT '02: Proceedings of the 11th international conference on Parallel architectures and compilation techniques, pages 30, IEEE Computer Society, 2002 |
| Optimizing SMT Processors for High Single-Thread Performance, , and (2003), in: The Journal of Instruction-Level Parallelism, 5 |
| Futexes are Tricky, (2005) |
E
| Simultaneous Multithreading: A Platform for Next-Generation Processors, , , , , and (1997), in: IEEE Micro, 17:5(12--19) |
[DOI] |
| Optimizing Compiler for the CELL Processor, , , , , , , , , , , , and , in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 161-172, 2005 |
[DOI] |
| Front-End Policies for Improved Issue Efficiency in SMT Processors, and , in: HPCA '03: Proceedings of the 9th International Symposium on High-Performance Computer Architecture, pages 31, IEEE Computer Society, 2003 |
| Partitioning Multi-Threaded Processors with a Large Number of Threads, , , and , in: ISPASS 2005: IEEE International Symposium on Performance Analysis of Systems and Software, 2005., pages 112-123, 2005 |
[DOI] |
F
| Fast synchronization on shared-memory multiprocessors: an architectural approach, , , , and (2005), in: J. Parallel Distrib. Comput., 65:10(1158--1170) |
[DOI] |
| Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures, , , and , in: PDP '05: Proceedings of the 13th Euromicro Conference on Parallel, Distributed and Network-Based Processing, pages 76--83, IEEE Computer Society, 2005 |
[DOI] |
| Concurrent programming without locks, and (2007), in: ACM Trans. Comput. Syst., 25:2(5) |
[DOI] |
G
| LU-GPU: Efficient Algorithms for Solving Dense Linear Systems on Graphics Hardware, , , and , in: Supercomputing '05: Proceedings of the 2005 ACM/IEEE conference on Supercomputing, IEEE Computer Society, 2005 |
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| Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors, and , in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 350--360, IEEE Computer Society, 2005 |
[DOI] |
| Database hash-join algorithms on multithreaded computer architectures, and , in: CF '06: Proceedings of the 3rd conference on Computing frontiers, Ischia, Italy, pages 241--252, ACM, 2006 |
[DOI] |
| Thread coloring: a scheduler proposal from user to hardware threads, and (2005), in: SIGOPS Oper. Syst. Rev., 39:2(54--70) |
[DOI] |
| A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies, , , and |
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| Using fine grain multithreading for energy efficient computing, , and , in: PPoPP '07: Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming, San Jose, California, USA, pages 259--269, ACM, 2007 |
[DOI] |
| Exploiting coarse-grained task, data, and pipeline parallelism in stream programs, , and (2006), in: SIGPLAN Not., 41:11(151--162) |
[DOI] |
| Stream Programming on General-Purpose Processors, and , in: MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, pages 343--354, IEEE Computer Society, 2005 |
[DOI] |
H
| Transactional coherence and consistency: simplifying parallel hardware and software, (2004), in: IEEE Micro, 24:6(92--103) |
[DOI] |
| A Single-Chip Multiprocessor, , and (1997), in: Computer, 30:9(79--85) |
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| Transactional Memory Coherence and Consistency, , , , , , , , , and , in: ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture, München, Germany, pages 102, IEEE Computer Society, 2004 |
| Transactional Memory: An Overview, , , , , , and , pages 8--29, IEEE Computer Society Press, 2007 |
[DOI] |
| Transactional Memory: Architectural Support For Lock-Free Data Structures, and , in: ISCA '93: Proceedings of the 20th annual international symposium on Computer architecture, 1993 |
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| The Microarchitecture of the Pentium 4 Processor, , , , , , and (2001), in: inteltechnologyjournal |
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I
| Slipstream execution mode for CMP-based multiprocessors, , and , in: HPCA '03: Proceedings of the IEEE 9th International Symposium on High Performance Computer Architecture, pages 179--190, 2003 |
[DOI] |
| Extending OpenMP to Support Slipstream Execution Mode, and , in: IPDPS '03: Proceedings of the 16th International Symposium on Parallel and Distributed Processing, pages 36.2, IEEE Computer Society, 2003 |
J
| Adaptive execution techniques for SMT multiprocessor architectures, , , and , in: PPoPP '05: Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, Chicago, IL, USA, pages 236--246, ACM, 2005 |
[DOI] |
K
| IBM Power5 chip: a dual-core multithreaded processor, (2004), in: IEEE Micro, 24:2(40-47) |
[DOI] |
| Coarse-Grained Thread Pipelining: A Speculative Parallel Execution Model for Shared-Memory Multiprocessors, and (2001), in: IEEE Trans. Parallel Distrib. Syst., 12:9(952--966) |
[DOI] |
| Lightweight lock-free synchronization methods for multithreading, , , , , , , and , in: ICS '06: Proceedings of the 20th annual international conference on Supercomputing, Cairns, Queensland, Australia, pages 361--371, ACM, 2006 |
[DOI] |
| The AMD Opteron processor for multiprocessor servers, (2003), in: IEEE Micro, 23:2(66-76) |
[DOI] |
| Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling., and , in: ICCD '04: Proceedings of the 2004 International Conference on Computer Design, pages 326--331, 2004 |
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| Compiler Based Pre-execution, , 2004 |
| Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors, , , , , , , , , and , in: CGO '04: Proceedings of the International Symposium on Code Generation and Optimization, Palo Alto, California, pages 27, IEEE Computer Society, 2004 |
| A study of source-level compiler algorithms for automatic construction of pre-execution code, and (2004), in: ACM Trans. Comput. Syst., 22:3(326--379) |
[DOI] |
| Design and evaluation of compiler algorithms for pre-execution, and , in: ASPLOS-X: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, pages 159--170, ACM Press, 2002 |
[DOI] |
| Using Program Slicing to Drive Pre-Execution on Simultaneous Multithreading Processors, and , University of Maryland, 2001 |
| Niagara: a 32-way multithreaded Sparc processor, , and (2005), in: IEEE Micro, 25:2(21-29) |
[DOI] |
| A Chip-Multiprocessor Architecture with Speculative Multithreading, and (1999), in: IEEE Trans. Comput., 48:9(866--880) |
[DOI] |
L
| Exploiting the performance of 32 bit floating point arithmetic in obtaining 64 bit accuracy (revisiting iterative refinement for linear systems), , , , , and , in: Supercomputing '06: Proceedings of the 2006 ACM/IEEE conference on Supercomputing, Tampa, Florida, pages 113, ACM, 2006 |
[DOI] |
| Efficient resources assignment schemes for clustered multithreaded processors, , and (2008), in: Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on(1-12) |
[DOI] |
| IBM POWER6 microarchitecture, , , , , , , , and (2007), in: IBM J. Res. Dev., 51:6(639--662) |
| Tuning compiler optimizations for simultaneous multithreading, , , , and , in: MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, Research Triangle Park, North Carolina, United States, pages 114--124, IEEE Computer Society, 1997 |
| Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading, , , , , and (1997), in: ACM Trans. Comput. Syst., 15:3(322--354) |
[DOI] |
| Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors, , in: ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, G\&\#246;teborg, Sweden, pages 40--51, ACM Press, 2001 |
[DOI] |
M
| A Study of a Simultaneous Multithreaded Processor Implementation, , and , in: Euro-Par '99: Proceedings of the 5th International Euro-Par Conference on Parallel Processing, pages 716--726, Springer-Verlag, 1999 |
| The Mitosis Speculative Multithreaded Architecture, , , , and , in: ParCo '05: Proceedings of the International Conference ParCo 2005, pages 27--38, 2005 |
| Thread-Spawning Schemes for Speculative Multithreading, and , in: HPCA '02: Proceedings of the IEEE 8th International Symposium on High Performance Computer Architecture, pages 55, IEEE Computer Society, 2002 |
| Speculative multithreaded processors, , and , in: ICS '98: Proceedings of the 12th annual international conference on Supercomputing, Melbourne, Australia, pages 77--84, ACM Press, 1998 |
[DOI] |
| Value prediction for speculative multithreaded architectures, , and , in: MICRO 32: Proceedings of the 32th annual ACM/IEEE international symposium on Microarchitecture, Haifa, Israel, pages 230--236, IEEE Computer Society, 1999 |
| Hyper-Threading Technology Architecture and Microarchitecture, , , , , , and (2002), in: Intel Technology Journal |
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| Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors., , and , in: IPDPS '05: Proceedings of the 19th International Symposium on Parallel and Distributed Processing, 2005 |
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| Montecito: a dual-core, dual-thread Itanium processor, (2005), in: IEEE Micro, 25:2(10-20) |
[DOI] |
| Algorithms for scalable synchronization on shared-memory multiprocessors, and (1995)(216--260) |
| ILP versus TLP on SMT, , , and , in: Supercomputing '99: Proceedings of the 1999 ACM/IEEE conference on Supercomputing, Portland, Oregon, United States, pages 37, ACM Press, 1999 |
[DOI] |
| Methods for Modeling Resource Contention on Simultaneous Multithreading Processors, , , and , in: ICCD '05: Proceedings of the 2005 International Conference on Computer Design, pages 373--380, IEEE Computer Society, 2005 |
[DOI] |
| Dynamic run-time architecture techniques for enabling continuous optimization, , , , , , , , , and , in: CF '05: Proceedings of the 2nd conference on Computing frontiers, Ischia, Italy, pages 211--220, ACM Press, 2005 |
[DOI] |
| Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling, (2001), in: Proceedings of the IEEE, 89:11(1560--1575) |
[DOI] |
N
| Pthreads for dynamic and irregular parallelism, and , in: Supercomputing '98: Proceedings of the 1998 ACM/IEEE conference on Supercomputing, San Jose, CA, pages 1--16, IEEE Computer Society, 1998 |
| Dynamic tiling for effective use of shared caches on multithreaded processors, (2006), in: International Journal of High Performance Computing and Networking, 2(22--35) |
[DOI] |
| Code and Data Transformations for Improving Shared Cache Performance on SMT Processors., , in: ISHPC, pages 54--69, 2003 |
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| Fast Synchronization on Scalable Cache-Coherent Multiprocessors using Hybrid Primitives, and , in: IPDPS '00: Proceedings of the 14th International Symposium on Parallel and Distributed Processing, pages 711, IEEE Computer Society, 2000 |
| The Adaptive Transactional Memory Test Platform: A Tool for Experimenting with Transactional Code for Rock, , and , in: TRANSACT 2008: 3rd ACM SIGPLAN Workshop on Transactional Computing, 2008 |
O
| Automatic Thread Extraction with Decoupled Software Pipelining, , , and , in: MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, pages 105--118, IEEE Computer Society, 2005 |
| A Survey of General-Purpose Computation on Graphics Hardware, , , , , , and (2005), in: Eurographics 2005, State of the Art Reports(21--51) |
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P
| Performance optimization of irregular codes based on the combination of reordering and blocking techniques, , , and (2005), in: Parallel Comput., 31:8+9(858--876) |
[DOI] |
Q
| Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices, , , , , and , in: PLDI '05: Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation, Chicago, IL, USA, pages 269--279, ACM Press, 2005 |
[DOI] |
R
| Compiler orchestrated prefetching via speculation and predication, , , and , in: ASPLOS-XI: Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, MA, USA, pages 189--198, ACM, 2004 |
[DOI] |
| Decoupled Software Pipelining with the Synchronization Array, , , and , in: PACT '04: Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pages 177--188, IEEE Computer Society, 2004 |
[DOI] |
| Mini-Threads: Increasing TLP on Small-Scale SMT Processors, , and , in: HPCA '03: Proceedings of the IEEE 9th International Symposium on High Performance Computer Architecture, pages 19, IEEE Computer Society, 2003 |
| Dependence based prefetching for linked data structures, , and , in: ASPLOS-VIII: Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, United States, pages 115--126, ACM Press, 1998 |
[DOI] |
| Evaluating the impact of simultaneous multithreading on network servers using real hardware, , , and (2005), in: SIGMETRICS Perform. Eval. Rev., 33:1(315--326) |
[DOI] |
S
| McRT-STM: a high performance software transactional memory system for a multi-core runtime, , , , and , in: PPoPP '06: Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, New York, New York, USA, pages 187--197, ACM, 2006 |
[DOI] |
| Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers, , , , , and , in: MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 235--246, IEEE Computer Society, 2006 |
[DOI] |
| Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture, and , in: HiPEAC, pages 353-368, 2008 |
[DOI] |
| Larrabee: a many-core x86 architecture for visual computing, , , , , , , , , , , , , and , in: SIGGRAPH '08: ACM SIGGRAPH 2008 papers, Los Angeles, California, pages 1--15, ACM, 2008 |
[DOI] |
| Architectural Support for Enhanced SMT Job Scheduling., , , and , in: PACT '04: Proceedings of the 13th international conference on Parallel architectures and compilation techniques, pages 63--73, 2004 |
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| The Microarchitecture of Superscalar Processors, and , 1995 |
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| Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors, , and , in: PACT '05: Proceedings of the 14th international conference on Parallel architectures and compilation techniques, pages 99--109, IEEE Computer Society, 2005 |
[DOI] |
| A Minimal Dual-Core Speculative Multi-Threading Architecture., , , and , in: ICCD '04: Proceedings of the 2004 International Conference on Computer Design, pages 360--367, 2004 |
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| Characterization and analysis of HMMER and SVM-RFE parallel bioinformatics applications, , in: Proceedings of the IEEE International Workload Characterization Symposium, pages 87--98, 2005 |
[DOI] |
| The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization, and , in: HPCA '98: Proceedings of the IEEE 4th International Symposium on High Performance Computer Architecture, pages 2--13, 1998 |
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T
| Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors, , and , in: EuroSys '07: Proceedings of the 2nd ACM SIGOPS/EuroSys European Conference on Computer Systems 2007, Lisbon, Portugal, pages 47--58, ACM, 2007 |
[DOI] |
| Exploring the Use of Hyper-Threading Technology for Multimedia Applications with Intel OpenMP Compiler, , , , , and , in: IPDPS '03: Proceedings of the 16th International Symposium on Parallel and Distributed Processing, pages 36.1, IEEE Computer Society, 2003 |
| Initial Observations of the Simultaneous Multithreading Pentium 4 Processor, and , in: PACT '03: Proceedings of the 12th international conference on Parallel architectures and compilation techniques, pages 26, IEEE Computer Society, 2003 |
| Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor, , , , , and , in: ISCA '96: Proceedings of the 23th annual international symposium on Computer architecture, Philadelphia, Pennsylvania, United States, pages 191--202, ACM Press, 1996 |
[DOI] |
| Simultaneous multithreading: maximizing on-chip parallelism, , and , in: ISCA '95: Proceedings of the 22th annual international symposium on Computer architecture, S. Margherita Ligure, Italy, pages 392--403, ACM Press, 1995 |
[DOI] |
| Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor, , , and , in: HPCA '99: Proceedings of the IEEE 5th International Symposium on High Performance Computer Architecture, pages 54, IEEE Computer Society, 1999 |
| Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy, , , and , in: MICRO 37: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, Portland, Oregon, pages 183--194, IEEE Computer Society, 2004 |
[DOI] |
V
| Understanding the Overhead of the Spin-Lock Loop in CMT Architectures, and , in: WIOSCA '08: In Procs. of Workshop on the Interaction between Operating Systems and Computer Architecture, 2008 |
| Buddy Threading in Distributed Applications on Simultaneous Multi-threading Processors, , Department of Computer Science, Raleigh, North California, 2005 |
W
| Helper threads via virtual multithreading, , , , , , , , , and (2004), in: IEEE Micro, 24:6(74--82) |
[DOI] |
| Helper threads via virtual multithreading on an experimental itanium2 processor-based platform, , , , , , , , , and (2004), in: SIGOPS Oper. Syst. Rev., 38:5(144--155) |
[DOI] |
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