High Performance Computing

The main objective of our group in this research area is to optimize critical software (mainly computationally or memory intensive applications) executing on high performance computing platforms. To achieve this intricate goal we need to delve as deeply as possible into the core characteristics of the applications and the underlying architecture. We focus on stencil computations, Sparse Matrix-Vector Multiplication SPMV, PDE solvers, graph algorithms and others. As far as the computing platforms are concerned, we work on PC clusters, multicore and multithreaded (SMT) microprocessors, and emerging architectures like GPGPUs and the CELL B/E.

Publications

• G. Goumas, K. Kourtis, N. Anastopoulos, V. Karakasis and N. Koziris, "Understanding the Performance of Sparse Matrix-Vector Multiplication," Proceedings of the 16th Euromicro International Conference on Parallel, Distributed and network-based Processing (PDP2008), Toulouse, France, 13-15 February, 2008
• K. Kourtis, G. Goumas, and N. Koziris, "Optimizing Sparse Matrix-Vector Multiplication Using Index and Value Compression," Proceedings of the ACM International Conference on Computing Frontiers, Ischia, Italy, 4-6 May, 2008
• N. Drosinos and N. Koziris, “Efficient Hybrid Parallelization of Tiled Algorithms on SMP Clusters,” International Journal of Computational Science and Engineering, 2007 (pdf)
• G. Goumas, N. Drosinos, M. Athanasaki and N. Koziris, “Message-Passing Code Generation for Non-rectangular Tiling Transformations,” Journal of Parallel Computing, pp. 711--732, 32(10), November 2006 (pdf)
• N. Drosinos, G. Goumas and N. Koziris, “Selecting the Tile Shape to Reduce the Total Communication Volume,” Proceedings of the 2006 International Parallel and Distributed Processing Symposium (IPDPS2006), Rhodes Island, Greece, 25-29 April, 2006 (pdf)
• M. Athanasaki, A. Sotiropoulos, G. Tsoukalas, N. Koziris, P. Tsanakas, “Hyperplane Grouping and Pipelined Schedules: How to Execute Tiled Loops Fast on Clusters of SMPs,” The Journal of Supercomputing, Volume 33, Issue 3, September 2005, pp. 197 - 226 (pdf)
• N. Drosinos and N. Koziris, “Performance Comparison of Pure MPI vs Hybrid MPI-OpenMP Parallelization Models on SMP Clusters,” Proceedings of the 18th International Parallel & Distributed Processing Symposium (IPDPS 2004), p. 15a (CD-ROM), Santa Fe, New Mexico, April 2004 (pdf)
• M. Athanasaki, E. Koukis, N. Koziris, “Scheduling of Tiled Nested Loops onto a Cluster with a Fixed Number of SMP Nodes,” 12th Euromicro Conference on Parallel, Distributed and Network based Processing (PDP '04), pp.424-433, A Coruna, Spain, February 11-13, 2004 (pdf)
• N. Koziris, A. Sotiropoulos, G. Goumas, “A Pipelined Schedule to Minimize Comple-tion Time for Loop Tiling with Computation and Communication Overlapping,” Journal of Parallel and Distributed Computing, Volume 63, Issue 11, November 2003, pp. 1138-1151 (pdf)
• M. Athanasaki, E. Koukis, N. Koziris, “Efficient Scheduling of Tiled Iteration Spaces onto a Fixed Size Parallel Architecture,” 9th Panhellenic Conference in Informatics, pp.178-192, Thessaloniki, Greece, November 21-23, 2003 (pdf)
• G. Goumas, M. Athanasaki and N. Koziris, “An Efficient Code Generation Technique for Tiled Iteration Spaces,” IEEE Transactions on Parallel and Distributed Systems, Vol. 14, No 10, October 2003 (pdf)
• A. Sotiropoulos, G. Tsoukalas, N. Koziris, “Efficient Utilization of Memory Mapped NICs onto Clusters using Pipelined Schedules,” Proceedings of the 2nd IEEE/ACM International Symposium on Cluster Computing and the Grid, Berlin, Germany, May 2002 (pdf)
• A. Sotiropoulos, G. Tsoukalas, N. Koziris, “Enhancing the Performance of Tiled Loop Execution onto Clusters using Memory Mapped Interfaces and Pipelined Schedules,” Proceedings of the 2002 Workshop on Communication Architecture for Clusters (CAC2002) held in conjunction with Int'l Parallel and Distributed Processing Symposium (IPDPS2002), Fort Lauderdale, Florida, April 2002 (pdf)
• M. Athanasaki, A. Sotiropoulos, G. Tsoukalas, N. Koziris, “Pipelined Scheduling of Tiled Nested Loops onto Clusters of SMPs using Memory Mapped Network Interfaces,” Proceedings of the ACM/IEEE Supercomputing 2002: High Performance Networking and Computing Conference (SC2002), Baltimore, Maryland, November 2002 (pdf)
• M. Athanasaki, A. Sotiropoulos, G. Tsoukalas, N. Koziris, “A Pipelined Execution of Tiled Nested Loops on SMPs with Computation and Communication Overlapping,” Proceedings of the Workshop on Compile/Runtime Techniques for Parallel Computing, held in conjunction with 2002 International Conference on Parallel Processing (ICPP-2002), Vancouver, Canada, August 2002 (pdf)
• A. Sotiropoulos, G. Tsoukalas, N. Koziris, “A Pipelined Execution of Tiled Nested Loops onto a Cluster of PCs using PCI-SCI NICs,” Proceedings of the 2001 SCI-Europe Conference, Dublin, Ireland, October 2001 (ps)
• G. Goumas, A. Sotiropoulos, N. Koziris, “Minimizing Completion Time for Loop Tiling with Computation and Communication Overlapping,” Proceedings of the 2001 International Parallel and Distributed Processing Symposium (IPDPS2001), IEEE Press, San Francisco, California, April 2001 (Best paper award) (pdf)